View HT1660-10_8030402.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ht1660 96 32 lcd controller for i/o mcu patented pat no. : 099352 rev. 1.70 1 november 9, 2010 features operating voltage: 2.7v~5.2v built-in 32khz rc oscillator external 32.768khz crystal oscillator or 32khz fre - quency source input standby current: <1 a at 3v, <2 aat5v internal resistor type: 1/6 bias or 1/5 bias, 1/32 duty, or 1/16 duty three selectable lcd frame frequencies: 64hz, 89hz or 170hz max. 96 32 patterns, 96 segments and 32 commons 112 segments and 16 commons selectable by com- mand method built-in bit-map display ram: 3072 bits (=96 32 bits) built-in internal resistor type bias generator six-wire interface (four data wires) eight kinds of time base/wdt selection time base or wdt overflow output r/w address auto increment built-in buzzer driver (2khz/4khz) power down command reduces power consumption software configuration feature data mode and command mode instructions three data accessing modes provides vlcd pin to adjust lcd operating voltage and max. vlcd voltage up to 7v provides three kinds of bias current programming control of tn-type and stn-type lcds 208-pin qfp package general description ht1660 is a peripheral device specially designed for i/o type mcu used to expand the display capability. the max. display segment of the device are 3072 patterns (96 segments and 32 commons). it also supports four data bits interface, buzzer sound, watchdog timer or time base timer functions. the ht1660 is a memory mapping and multi-function lcd controller. since the ht1660 can control tn-type (twisted nematic) or stn-type (super twisted nematic) lcds. the software configuration feature of the ht1660 make it suitable for multiple lcd applications including lcd modules and display subsystems. only six lines (cs ,wr , db0~db3) are required for the interface between the host controller and the ht1660. applications leisure products games personal digital assistant cellular phone global positioning system consumer electronics technical document tools information faqs application note
block diagram pin assignment ht1660 rev. 1.70 2 november 9, 2010 patented

! " # " ! $ ! % & " ' $ " ' ( )
* + , , # - . " " . . ! " ! $ % / 0 " 0

, 1
, 0

1
0
# '
2 1
'
2 $ 3 % 0

4 ! $ 3 ! % & 1
" ' $ 3 " ' ( ) 0

# - 0

4

5 6

& ) 7 & ) ) & ) 8 & ) % & ) 9 & ) & & ) $ & 8 ( & 8 : & 8 ; & 8 7 & 8 ) & 8 8 & 8 % & 8 9 & 8 & & 8 $ & % ( & % : & % ; & % 7 & % ) & % 8 & % % & % 9 & % & & % $ & 9 ( & 9 : & 9 ; & 9 7 & 9 ) & 9 8 & 9 % & 9 9 & 9 & & 9 $ & & ( & & : & & ; & & 7 & & ) & & 8 & & % & & 9 & & & & & $ & $ ( & $ : & $ ; & $ 7 & $ ) 9 $ : & 9 % 8 ) 7 ; : ( & $ & & & 9 & % & 8 & ) & 7 & ; & : & ( 9 $ 9 & 9 9 9 % 9 8 9 ) 9 7 9 ; 9 : 9 ( % $ % & % 9 % % % 8 % ) % 7 % ; % : % ( 8 $ 8 & 8 9 8 % 8 8 8 ) 8 7 8 ; 8 : 8 ( ) $ ) & ) 9 ) % 9 $ ; 9 $ 7 9 $ ) 9 $ 8 9 $ % 9 $ 9 9 $ & 9 $ $ & ( ( & ( : & ( ; & ( 7 & ( ) & ( 8 & ( % & ( 9 & ( & & ( $ & : ( & : : & : ; & : 7 & : ) & : 8 & : % & : 9 & : & & : $ & ; ( & ; : & ; ; & ; 7 & ; ) & ; 8 & ; % & ; 9 & ; & & ; $ & 7 ( & 7 : & 7 ; & 7 7 & 7 ) & 7 8 & 7 % & 7 9 & 7 & & 7 $ & ) ( & ) : & ) ; ) 8 ) ) ) 7 ) ; ) : ) ( 7 $ 7 & 7 9 7 % 7 8 7 ) 7 7 7 ; 7 : 7 ( ; $ ; & ; 9 ; % ; 8 ; ) ; 7 ; ; ; : ; ( : $ : & : 9 : % : 8 : ) : 7 : ; : : : ( ( $ ( & ( 9 ( % ( 8 ( ) ( 7 ( ; ( : ( ( & $ $ & $ & & $ 9 & $ % & $ 8 ! 9 9 ! 9 & ! 9 $ ! & ( ! & : ! & ; ! & 7 / / / / / / / / / " $ & 9 % . " " ! " # ! " ! . . # - , , & 9 % 8 $ $ $ . / / / / / / / / ! $ ! & ! 9 ! % ! 8 ! ) ! 7 ! & ) ! & 8 ! & % ! & 9 ! & & ! & $ ! ( ! : ! ; " ' 7 : " ' 7 ; " ' 7 7 " ' 7 ) " ' 7 8 " ' 7 % " ' 7 9 " ' 7 & " ' 7 $ " ' ) ( " ' ) : " ' ) ; " ' ) 7 " ' ) ) " ' ) 8 " ' ) % " ' ) 9 " ' ) & " ' ) $ " ' 8 ( " ' 8 : / / / / / / / / / / " ' 8 ; " ' 8 7 " ' 8 ) " ' 8 8 " ' 8 % " ' 7 ( " ' ; $ " ' ; & " ' ; 9 " ' ; % " ' ; 8 " ' ; ) " ' ; 7 " ' ; ; " ' ; : " ' ; ( " ' : $ " ' : & " ' : 9 " ' : % " ' : 8 " ' : ) " ' : 7 " ' : ; " ' : : " ' : ( " ' ( $ " ' ( & " ' ( 9 " ' ( % " ' ( 8 " ' ( ) / / / / / / / / / / / / / / / / ! % & ! % $ ! 9 ( ! 9 : ! 9 ; ! 9 7 ! 9 ) ! 9 8 ! 9 % " ' 9 7 " ' 9 ) " ' 9 8 " ' 9 % " ' 9 9 " ' 9 & " ' 9 $ " ' & ( " ' & : " ' & ; " ' & 7 " ' & ) " ' & 8 " ' & % " ' & 9 " ' & & " ' & $ " ' ( " ' : " ' ; " ' 7 " ' ) " ' 8 " ' % " ' 9 " ' & " ' $ / / / / / / / / / / / / / / / / " ' 8 9 " ' 8 & " ' 8 $ " ' % ( " ' % : " ' % ; " ' % 7 " ' % ) " ' % 8 " ' % % " ' % 9 " ' % & " ' % $ " ' 9 ( " ' 9 : " ' 9 ;
pad assignment chip size: 3555 5000 (m) 2 * the ic substrate should be connected to vss in the pcb layout artwork. ht1660 rev. 1.70 3 november 9, 2010 patented < $ 1 $ = & 9 % 8 ) 7 ; : ( & $ & & & 9 & % & 8 & ) & 7 & ; & : & ( 9 $ 9 & 9 9 9 % 9 8 9 ) 9 7 9 ; 9 : 9 ( % $ % & % 9 % % % 8 % ) % 7 % ; % : % ( 8 $ 8 & 8 9 8 % 8 8 8 ) 8 7 & & 7 & & ) & & 8 & & % & & 9 & & & & & $ & $ ( & $ : & $ ; & $ 7 & $ ) & $ 8 & $ % & $ 9 & $ & & $ $ ( ( ( : ( ; ( 7 ( ) ( 8 ( % ( 9 ( & ( $ : ( : : : ; : 7 : ) : 8 : % : 9 : & : $ ; ( ; : ; ; ; 7 ; ) ; 8 & & ; & & : & & ( & 9 $ & 9 && 9 9 & 9 % & 9 8 & 9 )& 9 7 & 9 ; & 9 : & 9 (& % $ & % & & % 9& % % & % 8& % ) & % 7& % ; & % : & % ( & 8 $ & 8 && 8 9 & 8 % & 8 8 & 8 )& 8 7 & 8 ; & 8 : & 8 ( 8 ; 8 : 8 ( ) $ ) & ) 9 ) % ) 8 ) ) ) 7 ) ; ) : ) ( 7 $ 7 & 7 9 7 % 7 8 7 ) 7 7 7 ; 7 : 7 ( ; $ ; & ; 9 ; % " ' 7 % " ' 7 8 " ' 7 ) " ' 7 7 " ' 7 ; " ' 7 : " ' 7 ( " ' ; $ " ' ; & " ' ; 9 " ' ; % " ' ; 8 " ' ; ) " ' ; 7 " ' ; ; " ' ; : " ' ; ( " ' : $ " ' : & " ' : 9 " ' : % " ' : 8 " ' : ) " ' : 7 " ' : ; " ' : : " ' : ( " ' ( $ " ' ( & " ' ( 9 " ' ( % " ' ( 8 " ' ( ) ! % & ! % $ ! 9 ( ! 9 : ! 9 ; ! 9 7 ! 9 ) ! 9 8 ! 9 % ! 9 9 ! 9 & ! 9 $ ! & ( ! & 7 ! & ; ! & : ! & ! $ . $ $ $ 8 % 9 & , , # - . . ! " ! ! " # . " " % 9 & " $ " ' & 7 " ' & ) " ' & 8 " ' & % " ' & 9 " ' & & " ' & $ " ' ( " ' : " ' ; " ' 7 " ' ) " ' 8 " ' % " ' 9 " ' & " ' $ ! & ) ! & 8 ! & % ! & 9 ! & & ! & $ ! ( ! : ! ; ! 7 ! ) ! 8 ! % ! 9 " ' & ; " ' & : " ' & ( " ' 9 $ " ' 9 & " ' 9 9 " ' 9 % " ' 9 8 " ' 9 ) " ' 9 7 " ' 9 ; " ' 9 : " ' 9 ( " ' % $ " ' % & " ' % 9 " ' % % " ' % 8 " ' % ) " ' % 7 " ' % ; " ' % : " ' % ( " ' 8 $ " ' 8 & " ' 8 9 " ' 8 % " ' 8 8 " ' 8 ) " ' 8 7 " ' 8 ; " ' 8 : " ' 8 ( " ' ) $ " ' ) & " ' ) 9 " ' ) % " ' ) 8 " ' ) ) " ' ) 7 " ' ) ; " ' ) : " ' ) ( " ' 7 $ " ' 7 & " ' 7 9
pad coordinates unit: m pad no. x y pad no. x y pad no. x y 1 1672.500 2305.000 51 789.900 2299.900 101 1672.500 405.900 2 1672.500 1901.700 52 694.900 2299.900 102 1672.500 500.900 3 1672.500 1806.700 53 589.300 2299.900 103 1672.500 595.900 4 1672.500 1711.700 54 494.300 2299.900 104 1672.500 690.900 5 1672.500 1616.700 55 388.700 2299.900 105 1672.500 785.900 6 1672.500 1521.700 56 293.700 2299.900 106 1672.500 880.900 7 1672.500 1426.700 57 190.500 2299.900 107 1672.500 975.900 8 1672.500 1331.700 58 95.000 2299.900 108 1672.500 1070.900 9 1672.500 1236.700 59 5.300 2299.900 109 1672.500 1165.900 10 1672.500 1141.700 60 111.400 2368.850 110 1672.500 1260.900 11 1672.500 1046.700 61 185.650 2268.850 111 1672.500 1355.900 12 1672.500 951.700 62 308.850 2309.400 112 1672.500 1450.900 13 1672.500 856.700 63 414.450 2309.400 113 1672.500 1545.900 14 1672.500 761.700 64 509.450 2309.400 114 1672.500 1640.900 15 1672.500 666.700 65 630.250 2285.250 115 1672.500 1735.900 16 1672.500 571.700 66 743.850 2285.250 116 1672.500 1830.900 17 1672.500 476.700 67 857.450 2285.250 117 1672.500 2305.000 18 1672.500 381.700 68 971.050 2285.250 118 1484.800 2395.000 19 1672.500 286.700 69 1084.650 2285.250 119 1389.800 2395.000 20 1672.500 191.700 70 1201.050 2368.850 120 1294.800 2395.000 21 1672.500 96.700 71 1323.050 2395.000 121 1199.800 2395.000 22 1672.500 1.700 72 1419.550 2395.000 122 1104.800 2395.000 23 1672.500 93.300 73 1666.450 2395.000 123 1009.800 2395.000 24 1672.500 188.300 74 1672.500 2159.100 124 914.800 2395.000 25 1672.500 283.300 75 1672.500 2064.100 125 819.800 2395.000 26 1672.500 378.300 76 1672.500 1969.100 126 724.800 2395.000 27 1672.500 473.300 77 1672.500 1874.100 127 629.800 2395.000 28 1672.500 568.300 78 1672.500 1779.100 128 534.800 2395.000 29 1672.500 663.300 79 1672.500 1684.100 129 439.800 2395.000 30 1672.500 758.300 80 1672.500 1589.100 130 344.800 2395.000 31 1672.500 853.300 81 1672.500 1494.100 131 249.800 2395.000 32 1672.500 948.300 82 1672.500 1399.100 132 154.800 2395.000 33 1672.500 1043.300 83 1672.500 1304.100 133 59.800 2395.000 34 1672.500 1138.300 84 1672.500 1209.100 134 35.200 2395.000 35 1672.500 1233.300 85 1672.500 1114.100 135 130.200 2395.000 36 1672.500 1328.300 86 1672.500 1019.100 136 225.200 2395.000 37 1672.500 1423.300 87 1672.500 924.100 137 320.200 2395.000 38 1672.500 1518.300 88 1672.500 829.100 138 415.200 2395.000 39 1672.500 1613.300 89 1672.500 734.100 139 510.200 2395.000 40 1672.500 1708.300 90 1672.500 639.100 140 605.200 2395.000 41 1672.500 1803.300 91 1672.500 544.100 141 700.200 2395.000 42 1672.500 1898.300 92 1672.500 449.100 142 795.200 2395.000 43 1672.500 1993.300 93 1672.500 354.100 143 890.200 2395.000 44 1672.500 2088.300 94 1672.500 259.100 144 985.200 2395.000 45 1672.500 2183.300 95 1672.500 164.100 145 1080.200 2395.000 46 1672.500 2278.300 96 1672.500 69.100 146 1175.200 2395.000 47 1208.250 2395.000 97 1672.500 25.900 147 1270.200 2395.000 48 1113.250 2395.000 98 1672.500 120.900 148 1365.200 2395.000 49 1018.250 2395.000 99 1672.500 215.900 149 1460.200 2395.000 50 895.500 2299.900 100 1672.500 310.900 ht1660 rev. 1.70 4 november 9, 2010 patented
pad description pad no. pad name i/o description 1~33 87~149 seg63~seg95 seg0~seg62 o lcd segment outputs 34~49 71~86 com31~com16 com0~com15 o lcd common outputs, under 112 16 command mode, com16~com31 will share to seg96~seg111. com31/seg96, com30/seg97, com29/ seg98....., com18/seg109, com17/seg110, com16/seg111 50 cs i chip selection input with pull-high resistor. when the cs is logic high, the data and command read from or write to the ht1660 are disabled. the serial interface circuit is also reset. but if the cs is at a logic low level and is input to the cs pad, the data and command transmission between the host controller and the ht1660 are all enabled. 51 rd i read clock input with pull-high resistor. data in the ram of the ht1660 are clocked out on the falling edge of the rd signal. the clocked out data will ap - pear on the data line. the host controller can use the next rising edge to latch the clocked out data. 52 wr i write clock input with pull-high resistor. data on the data line are latched into the ht1660 on the rising edge of the wr signal. 53~56 db0~db3 i/o parallel data input/output with a pull-high resistor 57 vss negative power supply for logic circuit, ground 58 59 osci osco i o the osci and osco pads are connected to a 32.768khz crystal in order to generate a system clock. if the system clock comes from an external clock source, the external clock source should be connected to the osci pad. but if an on-chip rc oscillator is selected, the osci and osco pads can be left open. 60 vdd positive power supply for logic circuit 61 vlcd i power supply for lcd driver circuit 62 irq o time base or watchdog timer overflow flag, nmos open drain output. 63, 64 bz, bz o 2khz or 4khz frequency output pair (tristate output buffer) 65~69 t1~t4, t000 i vary bias current pin it is usually not connected absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +5.5v storage temperature ............................ 50 cto125 c input voltage.............................v ss 0.3v to v dd +0.3v operating temperature........................... 25 cto75 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. ht1660 rev. 1.70 5 november 9, 2010 patented
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.7 5.2 v i dd1 operating current 3v no load/lcd on on-chip rc oscillator 150 250 a 5v 250 370 a i dd2 operating current 3v no load/lcd on crystal oscillator 135 200 a 5v 200 300 a i dd11 operating current 3v no load/lcd off on-chip rc oscillator 15 30 a 5v 50 70 a i dd22 operating current 3v no load/lcd off crystal oscillator 210 a 5v 310 a i stb standby current 3v no load, power down mode 1 a 5v 2 a v il input low voltage 3v db0~db3, wr ,cs ,rd 0 0.6 v 5v 0 1.0 v v ih input high voltage 3v db0~db3, wr ,cs ,rd 2.4 3v 5v 4.0 5v i ol1 bz, bz , irq sink current 3v v ol =0.3v 1.2 2.5 ma 5v v ol =0.5v 36 ma i oh1 bz, bz source current 3v v oh =2.7v 0.9 1.8 ma 5v v oh =4.5v 2 4 ma i ol2 db0~db3 sink current 3v v ol =0.3v 1.2 2.5 ma 5v v ol =0.5v 36 ma i oh2 db0~db3 source current 3v v oh =2.7v 0.9 1.8 ma 5v v oh =4.5v 2 4 ma i ol3 lcd common sink current 3v v ol =0.3v 80 160 a 5v v ol =0.5v 180 360 a i oh3 lcd common source current 3v v oh =2.7v 40 80 a 5v v oh =4.5v 90 180 a i ol4 lcd segment sink current 3v v ol =0.3v 50 100 a 5v v ol =0.5v 120 240 a i oh4 lcd segment source current 3v v oh =2.7v 30 60 a 5v v oh =4.5v 70 140 a r ph pull-high resistor 3v db0~db3, wr ,cs ,rd 150 250 410 k 5v 60 125 210 k ht1660 rev. 1.70 6 november 9, 2010 patented
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock 5v on-chip rc oscillator 24 32 40 khz f sys2 system clock crystal oscillator 32768 hz f sys3 system clock external clock source 32768 hz f lcd1 lcd frame frequency 5v on-chip rc oscillator 61/117 89/170 111/213 hz f lcd2 lcd frame frequency crystal oscillator 64 hz f lcd3 lcd frame frequency external clock source 64 hz t com lcd common period n: number of com n/f lcd sec f clk1 4-bit data clock (wr pin) 3v duty cycle 50% 150 khz 5v 300 khz f clk2 4-bit data clock (rd pin) 3v duty cycle 50% 75 khz 5v 150 khz t cs 4-bit interface reset pulse width (figure 3) cs 150 250 ns t clk wr ,rd input pulse width (figure 1) 3v write mode 3.34 s read mode 6.67 5v write mode 1.67 s read mode 3.34 t r ,t f rise/fall time serial data clock width (figure 1) 120 160 ns t su setup time for db to wr ,rd clock width (figure 2) 80 120 ns t h hold time for db to wr ,rd clock width (figure 2) 60 120 ns t su1 setup time for cs to wr ,rd clock width (figure 3)
100 ns t h1 setup time for cs to wr ,rd clock width (figure 3) 50 100 ns f tone2k tone frequency 5v on-chip rc oscillator 1.5 2 2.5 khz f tone4k tone frequency 5v on-chip rc oscillator 4 5 khz ht1660 rev. 1.70 7 november 9, 2010 patented
ht1660 rev. 1.70 8 november 9, 2010 patented ( $ > ) $ > & $ > / 1
2 ? 5 ? . figure 1 ) $ > .
) $ > / / 1
2 . figure 2 " / ) $ > ) $ > * 2 2 / 1
2 & & " . . figure 3 functional description system oscillator the ht1660 system clock is used to generate the time base/watchdog timer (wdt) clock frequency, lcd driving clock, and tone frequency. the clock source may be from an on-chip rc oscillator (32khz), a crystal oscillator (32.768khz), or an external 32khz clock by the s/w setting. the configuration of the system oscilla - tor is as shown. after the sys dis command is exe- cuted, the system clock will stop and the lcd bias generator will turn off. that command is available only for the on-chip rc oscillator or for the crystal oscillator. once the system clock stops, the lcd display will be- come blank, and the time base/wdt loses its function as well. the lcd off command is used to turn the lcd bias generator off. after the lcd bias generator switches off by issuing the lcd off command, using the sys dis command reduces power consumption, thus serving as a system power down command. but if the external clock source is chosen as the system clock, using the sys dis command can neither turn the oscillator off nor carry out the power down mode. the crystal oscillator option can be applied to connect an external frequency source of 32khz to the osci pin. in this case, the sys- tem fails to enter the power down mode, similar to the case in the external 32khz clock source operation. at the initial system power on, the ht1660 is at the sys dis state. ! " # ! " !
! % 9 ; 7 : @ a ' b
2
" % 9 2 @ a ! c

! % 9 2 @ a " 2 system oscillator configuration
ht1660 rev. 1.70 9 november 9, 2010 patented display memory ram structure the static display ram is organized into 768 4 bits and stores the display data. the contents of the ram are directly mapped to the contents of the lcd driver. data in the ram can be accessed by the read, write and read-modify-write commands. the following is a mapping from the ram to the lcd patterns. 00h 08h 10h 18h 20h--------- 2d8h 2e0h 2e8h 2f0h 2f8h com0 bit0 bit0 bit0 bit0 bit0 bit0 com1 bit1 bit1 bit1 bit1 bit1 bit1 com2 bit2 bit2 bit2 bit2 bit2 bit2 com3 bit3 bit3 bit3 bit3 bit3 bit3 01h 09h 11h 19h 21h--------- 2d9h 2e1h 2e9h 2f1h 2f9h com4 bit0 bit0 bit0 bit0 bit0 bit0 com5 bit1 bit1 bit1 bit1 bit1 bit1 com6 bit2 bit2 bit2 bit2 bit2 bit2 com7 bit3 bit3 bit3 bit3 bit3 bit3 02h 0ah 12h 1ah 22h--------- 2dah 2e2h 2eah 2f2h 2fah com8 bit0 bit0 bit0 bit0 bit0 bit0 com9 bit1 bit1 bit1 bit1 bit1 bit1 com10 bit2 bit2 bit2 bit2 bit2 bit2 com11 bit3 bit3 bit03 bit3 bit3 bit3 03h 0bh 13h 1bh 23h--------- 2dbh 2e3h 2ebh 2f3h 2fbh com12 bit0 bit0 bit0 bit0 bit0 bit0 com13 bit1 bit1 bit1 bit1 bit1 bit1 com14 bit2 bit2 bit2 bit2 bit2 bit2 com15 bit3 bit3 bit3 bit3 bit3 bit3 04h 0ch 14h 1ch 24h--------- 2dch 2e4h 2ech 2f4h 2fch com16 bit0 bit0 bit0 bit0 bit0 bit0 com17 bit1 bit1 bit1 bit1 bit1 bit1 com18 bit2 bit2 bit2 bit2 bit2 bit2 com19 bit3 bit3 bit3 bit3 bit3 bit3 05h 0dh 15h 1dh 25h--------- 2ddh 2e5h 2edh 2f5h 2fdh com20 bit0 bit0 bit0 bit0 bit0 bit0 com21 bit1 bit1 bit1 bit1 bit1 bit1 com22 bit2 bit2 bit2 bit2 bit2 bit2 com23 bit3 bit3 bit3 bit3 bit3 bit3 06h 0eh 16h 1eh 26h--------- 2deh 2e6h 2eeh 2f6h 2feh com24 bit0 bit0 bit0 bit0 bit0 bit0 com25 bit1 bit1 bit1 bit1 bit1 bit1 com26 bit2 bit2 bit2 bit2 bit2 bit2 com27 bit3 bit3 bit3 bit3 bit3 bit3 07h 0fh 17h 1fh 27h--------- 2dfh 2e7h 2efh 2f7h 2ffh com28 bit0 bit0 bit0 bit0 bit0 bit0 com29 bit1 bit1 bit1 bit1 bit1 bit1 com30 bit2 bit2 bit2 bit2 bit2 bit2 com31 bit3 bit3 bit3 bit3 bit3 bit3 seg0 seg1 seg2 seg3 seg92 seg93 seg94 seg95 96 32 selection mode ram mapping table
ht1660 rev. 1.70 10 november 9, 2010 patented 00h 04h 08h 0ch 10h--------- 1ach 1b0h 1b4h 1b8h 1bch com0 bit0 bit0 bit0 bit0 bit0 bit0 com1 bit1 bit1 bit1 bit1 bit1 bit1 com2 bit2 bit2 bit2 bit2 bit2 bit2 com3 bit3 bit3 bit3 bit3 bit3 bit3 01h 05h 09h 0dh 11h--------- 1adh 1b1h 1b5h 1b9h 1bdh com4 bit0 bit0 bit0 bit0 bit0 bit0 com5 bit1 bit1 bit1 bit1 bit1 bit1 com6 bit2 bit2 bit2 bit2 bit2 bit2 com7 bit3 bit3 bit3 bit3 bit3 bit3 02h 06h 0ah 0eh 12h--------- 1aeh 1b2h 1b6h 1bah 1beh com8 bit0 bit0 bit0 bit0 bit0 bit0 com9 bit1 bit1 bit1 bit1 bit1 bit1 com10 bit2 bit2 bit2 bit2 bit2 bit2 com11 bit3 bit3 bit3s bit3 bit3 bit3 03h 07h 0bh 0fh 13h--------- 1afh 1b3h 1b7h 1bbh 1bfh com12 bit0 bit0 bit0 bit0 bit0 bit0 com13 bit1 bit1 bit1 bit1 bit1 bit1 com14 bit2 bit2 bit2 bit2 bit2 bit2 com15 bit3 bit3 bit3 bit3 bit3 bit3 seg0 seg1 seg2 seg3 seg108 seg109 seg110 seg111 112 16 selection mode ram mapping table name command code function 112 16 mode x100 -0001-1111-xxxx change segment from 96 to 112 and common from 32 to 16 the default value after power on reset is 96 32 mode, set normal command will change 112 16 mode to 9632 mode. frame frequency ht1660 provides three kinds of frame frequency option by command code; 64hz, 89hz and 170hz respectively. frame 64hz provides 64hz frame frequency. frame 89hz provides 89hz frame frequency. frame 170hz provides 170hz frame frequency. name command code function frame 170hz x 100 -0001-1000-xxxx select 170hz frame frequency frame 89hz x 100 -0001-1101-xxxx select 89hz frame frequency frame 64hz x 100 -0001-1110-xxxx select 64hz frame frequency frame frequency selection command code time base and watchdog timer wdt the time base generator and wdt share the same counter which is divided by 256. the irq clock can be programmed as 1hz, 2hz, ...., 128hz output. timer dis/en/clr, wdt dis/en/clr and irq en/dis are independent from each other. once the wdt time-out occurs, the irq pin will remain at a logic low level until the clr wdt or the irq dis command is issued. if an external clock is selected as the system frequency source, the sys dis command turns out invalid and the power down mode fails to be carried out until the external clock source is removed.
ht1660 rev. 1.70 11 november 9, 2010 patented buzzer tone output a simple tone generator is implemented in the ht1660. the tone generator can output a pair of differential driv - ing signals on the bz and bz which are used to generate a single tone. by executing the tone 4k and tone 2k commands there are two tone frequency outputs selectable that can turn on the tone output. the tone 4k and tone 2k commands set the tone frequency to 4khz and 2khz, re - spectively. the tone output can be turned off by invoking the tone off command. the tone outputs, namely bz and bz , are a pair of differential driving outputs used to drive a piezo buzzer. once the system is disabled or the tone output is inhibited, the bz and the bz outputs will remain at low level. command format the ht1660 can be configured by software setting. there are two mode commands to configure the ht1660 resource and to transfer the lcd display data. the configuration mode of the ht1660 is called com - mand mode, and its command mode id is 100. the command mode consists of a system configuration command, a system frequency selection command, an lcd configuration command, a tone frequency selec - tion command, a bias current selection command, a timer/wdt setting command, and an operating com - mand. the data mode, on the other hand, includes read, write, and read-modify-write opera - tions. the following are the data mode id and the command mode id: operation mode id read data 110 write data 101 read-modify-write data 101 command command 100 if successive commands have been issued, the com - mand mode id can be omitted. while the system is op - erating in the non-successive command or the non-successive address data mode, the cs pin should be set to 1 and the previous operation mode will also be reset. the cs pin returns to 0 , so a new operation mode id should be issued first.
' / # " # -
' / # " ? -
2
" 8 9 ) 7

# - . # '
' / # " time base and wdt configurations name command code function tone off x100 -0000-1000-xxxx turn-off tone output tone 4k x100 -0001-0000-xxxx turn-on tone output, tone frequency is 4khz tone 2k x100 -0001-0001-xxxx turn-on tone output, tone frequency is 2khz buzzer tone output command code the following are the data mode id and the command id: operation mode id read data 110 write data 101 read-modify-write data 101 command command 100 if successive commands have been issued, the command mode id can be omitted. while the system is operating in the non-successive address data mode, the cs pin should be set 1 and the previous operation mode will also be reset. the cs pin returns to 0, so a new operation mode id should be issued first.
ht1660 rev. 1.70 12 november 9, 2010 patented bias generator the ht1660 bias voltage belongs to internal resistor type. it provides two kinds of bias option named 1/6 bias and 1/5 bias respectively. it also provides three kinds of bias current option by programming to suitably drive an lcd panel. the three kinds of bias current are large, middle, and small, respectively. usually, large panel lcd can be excellently displayed by large bias current. relatively, it consumes large current when lcd on command is used. small bias current provides low power consumption during on condition when the lcd is normally displayed. the following are the reference value table. when the bias current for lcd is more than large bias current setting. it is recommended to add external cir - cuit to increase driving current. interfacing only six lines are required to interface with the ht1660. the cs line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the ht1660. if the cs pin is set to 1, the data and command issued between the host controller and the ht1660 are first disabled and then initialized. before issuing a mode command or mode switching, a high level pulse is required to initialize the serial inter - face of the ht1660. the db0~db3 are the 4-bit parallel data input/output lines. data to be read or written or commands to be written have to pass through the db0~db3 lines. the rd line is the read clock input. data in the ram are clocked out on the falling edge of the rd signal, and the clocked out data will then appear on the db0~db3 lines. it is recommended that the host controller read correct data during the interval between the rising edge and the next falling edge of the rd signal. the wr line is the write clock input. the data, ad - dress, and command on the db0~db3 lines are all clocked into the ht1660 on the rising edge of the wr signal. there is an optional irq line to be used as an in - terface between the host controller and the ht1660. the irq pin can be selected as a timer output or a wdt overflow flag output by the s/w setting. the host con - troller can perform the time base or the wdt function by connecting with the irq pin of the ht1660. bias vlcd large bias current middle bias current small bias current 1/5 3v 165a7 0 a3 0 a 5v 270a 110a5 0 a 1/6 3v 140a5 5 a2 5 a 5v 225a9 0 a4 0 a

internal resistor type bias generator configurations note: the voltage applied to v lcd pin must be equal to or lower than 7v. adjust vr to fit lcd display.
timing diagrams read mode (command id code :110) ht1660 rev. 1.70 13 november 9, 2010 patented & )
. & 9 % 8 $ $ $ 2 & 7
9 & 9 % 8 $ $ $ 2 . . . increase driver current configurations note: the external resistors are used to increment the driving current. and the external capacitors are used to keep the bias voltage stable. % " % % % % % % % % % % % % % % % % ; % % 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 & 7 9 9 & $ & & & & & & & & & & & & & & & & & ) & & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 8 $ $
< =
#

< e & ) =
< e & 8 =
< e & % =
< e & 9 =
< e & & =
< e & $ =
< e ( =
< e : =
< e ; =
< e 7 =
< e ) =
< e 8 =
< e % =
< e 9 =
< e & =
< =
#
< "

= < "

= f f f : ( ; % f f 7 9 & f ) & & ( 8 $ $ :
< =
< =
< =
< =
write mode (command id code :101) read-modify-write mode (command id code :101) ht1660 rev. 1.70 14 november 9, 2010 patented % " % % % % % % % % % % % % % % % % ; % % 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 & 7 9 9 & $ & & & & & & & & & & & & & & & & $ ) & & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ & 8 $ $
< =
#

< e & ) =
< e & 8 =
< e & % =
< e & 9 =
< e & & =
< e & $ =
< e ( =
< e : =
< e ; =
< e 7 =
< e ) =
< e 8 =
< e % =
< e 9 =
< e & =
< =
#
< "

= < "

= f f f : ( ; % f f 7 9 & f ) & $ ( 8 $ & :
< =
< =
< =
< = % " % % % % % % % % % % % % % % % % ; % % 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 & 7 9 9 & $ & & & & & & & & & & & & & & & & & ) & & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 8 $ $
< =
#

< e ; =
< e ; =
< e 7 =
< e 7 =
< e ) =
< e ) =
< e 8 =
< e 8 =
< e % =
< e % =
< e 9 =
< e 9 =
< e & =
< e & =
< =
< =
#
< "

= < "

= f f f : ( ; % f f 7 9 & f ) & ( 8 $ :
< =
< =
< =
< = % 9 & $ & $
command mode (command id code :100) note: x stands for don t care application circuits host controller with an ht1660 display system *note: the connection of irq and rd pin can be selected depending on the mcu. adjust vr to fit lcd display adjust r (external pull-high resistance) to fit user s time base clock. it is recommended that the internal equivalent capacitance between seg and com of lcd panel should be lower than 10pf. (lcr meter test condition: frequency in 1khz) ht1660 rev. 1.70 15 november 9, 2010 patented % " f f ; % 9 & & 7 9 f & $ $ $ ) & f $ $
#

#
< "
= 8 $ f
)
8
%
9
&
< "
= ; % 7 9 ) & 8 $ f f f f f f f f ; % 7 9 ) & 8 $ f f f f f f f f ; % 7 9 ) & 8 $ f f f f f f f f ; % 7 9 ) & 8 $ f f f f f f f f ; % 7 9 ) & 8 $ f f f f f # - $ 3 % g ! c
! " ! " # ! " ! 2
! ' b
2
&
< % 9 2 @ a = ' b
2
9
< % 9 2 @ a = " % 9 ; 7 : @ a , , ! $
3
! % & " ' $ 3 " ' ( ) g & 7

& )
1 & % 9

& & 7
g . g . d a b h ; .
instruction set summary name command code d/c function def. read x110-xxa9a8-a7a6a5a4-a3a2a1a0- d3d2d1d0 d read data from the ram write x101-xxa9a8-a7a6a5a4-a3a2a1a0- d3d2d1d0 d write data to the ram read-modify- write x101-xxa9a8-a7a6a5a4-a3a2a1a0- d3d2d1d0 d read and write data to the ram sys dis x100-0000-0000-xxxx-xxxx c turn off both system oscillator and lcd bias generator yes sys en x100-0000-0001-xxxx-xxxx c turn on system oscillator lcd off x100-0000-0010-xxxx-xxxx c turn off lcd display yes lcd on x100-0000-0011-xxxx-xxxx c turn on lcd display timer dis x100-0000-0100-xxxx-xxxx c disable time base output yes wdt dis x100-0000-0101-xxxx-xxxx c disable wdt time-out flag output yes timer en x100-0000-0110-xxxx-xxxx c enable time base output wdt en x100-0000-0111-xxxx-xxxx c enable wdt time-out flag output tone off x100-0000-1000-xxxx-xxxx c turn off tone outputs yes clr timer x100-0000-1101-xxxx-xxxx c clear the contents of the time base generator clr wdt x100-0000-1111-xxxx-xxxx c clear the contents of the wdt stage tone 4k x100-0001-0000-xxxx-xxxx c turn on tone output, tone frequency output: 4khz tone 2k x100-0001-0001-xxxx-xxxx c turn on tone output, tone frequency output: 2khz irq dis x100-0001-0010-xxxx-xxxx c disable irq output yes irq en x100-0001-0011-xxxx-xxxx c enable irq output rc 32k x100-0001-0100-xxxx-xxxx c system clock source, on-chip rc oscillator yes ext (x tal) x100-0001-0101-xxxx-xxxx c system clock source, external 32khz clock source or crystal oscillator 32.768khz large bias x100-0001-0110-xxxx-xxxx c large bias current option yes middle bias x100-0001-0111-xxxx-xxxx c middle bias current option small bias x100-0001-1000-xxxx-xxxx c small bias current option bias 1/6 x100-0001-1010-xxxx-xxxx c lcd 1/6 bias option yes bias 1/5 x100-0001-1001-xxxx-xxxx c lcd 1/5 bias option frame 170hz x100-0001-1100-xxxx-xxxx c selects 170hz frame frequency frame 89hz x100-0001-1101-xxxx-xxxx c selects 89hz frame frequency frame 64hz x100-0001-1110-xxxx-xxxx c selects 64hz frame frequency yes select 112 16 x100-0001-1111-xxxx-xxxx c this command will change segment from 96 to 112 and common from 32 to 16 f1 x100-1010-0000-xxxx-xxxx c time base clock output: 1hz the wdt time-out flag after: 4s f2 x100-1010-0001-xxxx-xxxx c time base clock output: 2hz the wdt time-out flag after: 2s f4 x100-1010-0010-xxxx-xxxx c time base clock output: 4hz the wdt time-out flag after: 1s ht1660 rev. 1.70 16 november 9, 2010 patented
name command code d/c function def. f8 x100-1010-0011-xxxx-xxxx c time base clock output: 8hz the wdt time-out flag after: 1/2s f16 x100-1010-0100-xxxx-xxxx c time base clock output: 16hz the wdt time-out flag after: 1/4s f32 x100-1010-0101-xxxx-xxxx c time base clock output: 32hz the wdt time-out flag after: 1/8s f64 x100-1010-0110-xxxx-xxxx c time base clock output: 96hz the time-out flag after: 1/16s f128 x100-1010-0111-xxxx-xxxx c time base clock output: 128hz the wdt time-out flag after: 1/32s yes test x100-1111-1111-xxxx-xxxx c test mode, user don t use. normal x100-1111-1110-xxxx-xxxx c normal mode, 96 32 mode will be set yes note: x stands for don t care a9~a0: ram address d3~d0: ram data d/c: data/command mode def.: power-on reset default all the bold forms, namely 110, 10 1, and 10 0, are mode commands. of these, 10 0 indicates the command mode id. if successive commands have been issued, the command mode id except for the first command will be omitted. the tone frequency source and the time base/wdt clock frequency source can be derived from an on-chip 32khz rc oscillator, a 32.768khz crystal oscillator, or an external 32khz clock. calculation of the fre - quency is based on the system frequency sources as stated above. it is recommended that the host controller should initialize the ht1660 after power-on reset, otherwise, power on reset may fail, which in turn leads to the malfunctioning of the ht1660. ht1660 rev. 1.70 17 november 9, 2010 patented
package information 208-pin qfp (28mm 28mm) outline dimensions symbol dimensions in inch min. nom. max. a 1.220 1.236 b 1.098 1.106 c 1.220 1.236 d 1.098 1.106 e 0.020 f 0.008 g 0.098 0.122 h 0.134 i 0.004 j 0.014 0.026 k 0.004 0.008 07 ht1660 rev. 1.70 18 november 9, 2010 patented & ) ; & ) 7 9 $ : & & $ ) ) 9 ) % & $ 8 ' * @ # i ?
symbol dimensions in mm min. nom. max. a 31.00 31.40 b 27.90 28.10 c 31.00 31.40 d 27.90 28.10 e 0.50 f 0.20 g 3.10 3.40 h 3.70 i 0.10 j 0.35 0.65 k 0.10 0.20 07 ht1660 rev. 1.70 19 november 9, 2010 patented
ht1660 rev. 1.70 20 november 9, 2010 patented copyright 2010 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

▲Up To Search▲

Price & Availability of HT1660-10

	To Download HT1660-10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .